Invention Grant
US08097542B2 Etch stop layer of reduced thickness for patterning a dielectric material in a contact level of closely spaced transistors
有权
用于图案化紧密间隔晶体管的接触电平的介电材料的减小厚度的蚀刻停止层
- Patent Title: Etch stop layer of reduced thickness for patterning a dielectric material in a contact level of closely spaced transistors
- Patent Title (中): 用于图案化紧密间隔晶体管的接触电平的介电材料的减小厚度的蚀刻停止层
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Application No.: US12260147Application Date: 2008-10-29
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Publication No.: US08097542B2Publication Date: 2012-01-17
- Inventor: Karsten Wieczorek , Manfred Horstmann , Peter Huebler , Kerstin Ruttloff
- Applicant: Karsten Wieczorek , Manfred Horstmann , Peter Huebler , Kerstin Ruttloff
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102008011928 20080229
- Main IPC: H01L21/31
- IPC: H01L21/31
Abstract:
In a dual stress liner approach, an intermediate etch stop material may be provided on the basis of a plasma-assisted oxidation process rather than by deposition so the corresponding thickness of the etch stop material may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices.
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