Invention Grant
- Patent Title: Integrated circuit having wiring layer and a pattern in which a gap is formed and method for manufacturing same
- Patent Title (中): 具有布线层的集成电路和形成间隙的图案及其制造方法
-
Application No.: US12379793Application Date: 2009-03-02
-
Publication No.: US08097951B2Publication Date: 2012-01-17
- Inventor: Katsushi Matsuda
- Applicant: Katsushi Matsuda
- Applicant Address: JP Moriguchi-shi JP Gunma
- Assignee: Sanyo Electric Co., Ltd.,Sanyo Semiconductor Co., Ltd.
- Current Assignee: Sanyo Electric Co., Ltd.,Sanyo Semiconductor Co., Ltd.
- Current Assignee Address: JP Moriguchi-shi JP Gunma
- Agency: Oliff & Berridge, PLC
- Priority: JP2008-052894 20080304
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
When an integrated circuit having an interlayer insulation film built up on top of a wiring layer is subjected to a heat treatment, it is unlikely that a void formed in the interlayer insulation film will rupture in a portion wherein are connected a narrow gap between wirings and a wide open part contiguous therewith. A corner part of a wiring positioned at a portion where a gap and an open part are connected is chamfered, and an end part of the gap is shaped so as to widen toward the open part. Providing the widening end part in the gap thus mitigates any discontinuity in the built up interlayer insulation film between the gap and the open part. As a result, the interlayer insulation film does not readily seal off an end of a void formed in the gap.
Public/Granted literature
- US20090224373A1 Integrated circuit and method for manufacturing same Public/Granted day:2009-09-10
Information query
IPC分类: