Invention Grant
- Patent Title: System and method for instruction latency reduction in graphics processing
- Patent Title (中): 图形处理中指令延迟减少的系统和方法
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Application No.: US12035667Application Date: 2008-02-22
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Publication No.: US08098251B2Publication Date: 2012-01-17
- Inventor: Lin Chen
- Applicant: Lin Chen
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Matthew J. Evans; James R. Gambale, Jr.
- Main IPC: G06F15/16
- IPC: G06F15/16 ; G06F9/45
Abstract:
A system, method and apparatus are disclosed, in which an instruction scheduler of a compiler, e.g., a shader compiler, reduces instruction latency based on a determined instruction distance between a dependent predecessor and successor instructions.
Public/Granted literature
- US20090213128A1 SYSTEM AND METHOD FOR INSTRUCTION LATENCY REDUCTION IN GRAPHICS PROCESSING Public/Granted day:2009-08-27
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