A processor for image capture and printing has a RISC core. A four-way parallel VLIW vector processor is connected to the RISC core via a suitable data cache. The vector processor has four processing units interconnected with a crossbar switch. A memory interface is connected to the vector processor to permit interfacing between the data cache and a memory. Interfacing circuitry is operatively connected to the vector processor. The interfacing circuitry includes at least an image sensor interface to permit interfacing between components of the processor and an image sensor and a printhead interface to permit interfacing between components of the processor and an inkjet printhead.