Invention Grant
- Patent Title: Method and apparatus for gate training in memory interfaces
- Patent Title (中): 存储器接口中门训练的方法和装置
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Application No.: US12413998Application Date: 2009-03-30
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Publication No.: US08098535B2Publication Date: 2012-01-17
- Inventor: John MacLaren , Anne Espinoza
- Applicant: John MacLaren , Anne Espinoza
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patent Venture Group
- Agent Joe A. Brock, II
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C8/18

Abstract:
An invention is provided for gate training in memory interfaces. The invention includes adding a coarse delay to a gate assert time, where the coarse delay is a predefined period of time and the gate assert time is a time when a data strobe gate signal is asserted. Next, the a data strobe signal is repeatedly sampled at the gate assert time until a rising edge of the data strobe signal is found, wherein a fine delay is added to the gate assert time between sampling of the data strobe signal. The fine delay is a period of time shorter than the coarse delay. Once the rising edge is found, the coarse delay is removed from the gate assert time, thus setting the gate assert time centrally within the preamble of the data strobe signal.
Public/Granted literature
- US20100246290A1 METHOD AND APPARATUS FOR GATE TRAINING IN MEMORY INTERFACES Public/Granted day:2010-09-30
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