Invention Grant
- Patent Title: Muting circuit
- Patent Title (中): 静音电路
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Application No.: US11858848Application Date: 2007-09-20
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Publication No.: US08098847B2Publication Date: 2012-01-17
- Inventor: Akio Watanabe
- Applicant: Akio Watanabe
- Applicant Address: US AZ Phoenix JP Gunma
- Assignee: Semiconductor Components Industries, LLC,Sanyo Semiconductor Co., Ltd.
- Current Assignee: Semiconductor Components Industries, LLC,Sanyo Semiconductor Co., Ltd.
- Current Assignee Address: US AZ Phoenix JP Gunma
- Agency: SoCal IP Law Group LLP
- Agent Steven C. Sereboff; John E. Gunther
- Priority: JP2006-256163 20060921
- Main IPC: H04B15/00
- IPC: H04B15/00

Abstract:
A muting circuit comprising: a DC offset eliminating unit including an HPF (High Pass Filter) constituted by a first operational amplifier to eliminate a DC offset component of an AC input signal, the DC offset eliminating unit being configured to output an output signal obtained by eliminating the DC offset component of the AC input signal; a muting signal generating unit including a second operational amplifier configured to generate a second DC offset identical in level to a first DC offset at the first operational amplifier, the muting signal generating unit being configured to output a muting signal indicative of the second DC offset by fixing input to the second operational amplifier at a predetermined DC level; and a selecting unit configured to select and output the output signal when muting is not executed, and to select and output the muting signal when muting is executed.
Public/Granted literature
- US20080075301A1 Muting Circuit Public/Granted day:2008-03-27
Information query