A method, system and apparatus of shared bus architecture are disclosed. In one embodiment, a method controlling set of multiplexers using an arbiter circuit per transaction, selecting one of a memory clock and a host clock based on an arbitration status, driving a final output on an interface to provide glitchless switching of an interface signal, connecting the interface signal to a tri-state buffer, and setting the direction of a data and address bus based on the connection of the interface signal to the tri-state buffer. The method may include applying a fair arbitration policy to ensure that none of the devices coupled to the interface signal and application threads running on processor requiring data from different devices are starved.