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US08099562B2 Scalable interface for a memory array 失效
内存阵列的可扩展接口

Scalable interface for a memory array
Abstract:
A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests.
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