Invention Grant
US08099639B2 Failure analysis method, failure analysis system, and memory macro system
有权
故障分析方法,故障分析系统和内存宏系统
- Patent Title: Failure analysis method, failure analysis system, and memory macro system
- Patent Title (中): 故障分析方法,故障分析系统和内存宏系统
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Application No.: US12563881Application Date: 2009-09-21
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Publication No.: US08099639B2Publication Date: 2012-01-17
- Inventor: Mami Kodama
- Applicant: Mami Kodama
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2009-034330 20090217
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11R31/28

Abstract:
Configuration information including number of normal cell areas and number of spare cell areas arranged in a memory macro and a size of each cell area is extracted from circuit design information, and electrical test results of the normal cell areas and the spare cell areas arranged in the memory macro are collected. Arrangement information corresponding to a collection order of the electrical test results is converted to a two-dimensional coordinate value for two-dimensionally displaying the arrangement information corresponding to a collection order of the electrical test results in a unit of cell area in association with a physical layout of a memory cell in the memory macro based on the configuration information. The collected electrical test results are displayed based on the two-dimensional coordinate value so that the normal cell areas and the spare cell areas can be distinguished.
Public/Granted literature
- US20100211836A1 FAILURE ANALYSIS METHOD, FAILURE ANALYSIS SYSTEM, AND MEMORY MACRO SYSTEM Public/Granted day:2010-08-19
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