A shared diagnosis method may be for an electronic integrated system embedding a plurality of memory units associated with Built In Self Test (BIST) hardware portions for executing a test on memory locations of the memory units. A FAIL signal may be provided from the hardware portions, together with the memory locations of the memory units on which the test is executed. The method may include loading of address, state and data signals, generated during the test on the memory locations, in a series of bitmapping registers and supplied by multiplexer devices, which receive as inputs the address, state, and data signals from the memory units and from the hardware portions. The enabling for the loading of the bitmapping registers is through the processing of a Fail signal in a counter supplied by a multiplexer device receiving the Fail signals from the hardware portions.