Invention Grant
US08099697B2 Hardware logic verification support apparatus, verification support method and computer product
有权
硬件逻辑验证支持设备,验证支持方法和计算机产品
- Patent Title: Hardware logic verification support apparatus, verification support method and computer product
- Patent Title (中): 硬件逻辑验证支持设备,验证支持方法和计算机产品
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Application No.: US12484762Application Date: 2009-06-15
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Publication No.: US08099697B2Publication Date: 2012-01-17
- Inventor: Akio Matsuda , Ryosuke Oishi
- Applicant: Akio Matsuda , Ryosuke Oishi
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Greer, Burns & Crain, Ltd.
- Priority: JP2008-229674 20080908
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50

Abstract:
A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a combinational circuit to be verified; extracting, from the hardware description, a conditional branch description expressing conditional branch processing; identifying, from among conditional branch descriptions extracted at the extracting of a conditional branch description and based on a description sequence in the hardware description, a combination of conditional branch descriptions having a hierarchical relation; extracting, from among combinations of conditional branch descriptions identified at the identifying, a combination having a potential to satisfy a specified condition; creating a simulation program that causes the specified condition for the conditional branch descriptions included in the combination extracted at the extracting of the combination to be satisfied; and outputting, as assertion information of the combinational circuit, the simulation program created for each combination at the creating.
Public/Granted literature
- US20100064266A1 VERIFICATION SUPPORT APPARATUS, VERIFICATION SUPPORT METHOD, AND COMPUTER PRODUCT Public/Granted day:2010-03-11
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