Invention Grant
- Patent Title: Wiring substrate, semiconductor device and manufacturing method thereof
- Patent Title (中): 配线基板,半导体装置及其制造方法
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Application No.: US12371269Application Date: 2009-02-13
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Publication No.: US08102005B2Publication Date: 2012-01-24
- Inventor: Hiroko Yamamoto , Osamu Nakamura
- Applicant: Hiroko Yamamoto , Osamu Nakamura
- Applicant Address: JP
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP
- Agency: Husch Blackwell LLP
- Priority: JP2004-175833 20040614
- Main IPC: H01L21/70
- IPC: H01L21/70

Abstract:
The present invention provides a method for forming a wiring having a minute shape on a large substrate with a small number of steps, and further a wiring substrate formed by the method. Moreover, the present invention provides a semiconductor device in which cost reduction and throughput improvement are possible due to the small number of steps and reduction of materials and which has a semiconductor element with a minute structure, and further a manufacturing method thereof. According to the present invention, a composition including metal particles and organic resin is irradiated with laser light and a part of the metal particles is baked to form a conductive layer typified by a wiring, an electrode or the like over a substrate. Further, a semiconductor device having the baked conductive layer as a wiring or an electrode is formed.
Public/Granted literature
- US20090179230A1 Wiring Substrate, Semiconductor Device and Manufacturing Method Thereof Public/Granted day:2009-07-16
Information query
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