Invention Grant
- Patent Title: Via design for flux residue mitigation
- Patent Title (中): 通过设计减少助焊剂残留
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Application No.: US11645908Application Date: 2006-12-27
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Publication No.: US08102057B2Publication Date: 2012-01-24
- Inventor: Alexander Leon , Rosa Reinosa , Michael David Carothers , Glen Griffiths
- Applicant: Alexander Leon , Rosa Reinosa , Michael David Carothers , Glen Griffiths
- Applicant Address: US TX Houston
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Houston
- Main IPC: B32B3/24
- IPC: B32B3/24

Abstract:
Provided is an electrically conductive via for reducing flux residue. The via has a first aperture having a first diameter size. The via further has a second aperture having a second diameter size. A chamber is disposed between the first aperture and the second aperture, the chamber having a third diameter size. At least one of the diameters being of a different dimension than the other two. In addition, the via may also provide improved test point access in addition to reducing flux residue.
Public/Granted literature
- US20080160252A1 Via design for flux residue mitigation Public/Granted day:2008-07-03
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