Invention Grant
- Patent Title: Semiconductor integrated circuits with power reduction mechanism
- Patent Title (中): 半导体集成电路具有功率降低机制
-
Application No.: US12645784Application Date: 2009-12-23
-
Publication No.: US08106678B2Publication Date: 2012-01-31
- Inventor: Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
- Applicant: Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP
- Priority: JP05-000973 19930107; JP05-015236 19930202
- Main IPC: H03K19/003
- IPC: H03K19/003 ; H03K17/16

Abstract:
A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.
Public/Granted literature
- US20100109702A1 SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM Public/Granted day:2010-05-06
Information query