A semiconductor memory includes a memory cell having a cell transistor and a selection transistor, a control gate line coupled to a gate electrode of the cell transistor, a selection gate line coupled to a gate electrode of the selection transistor, a selection gate driver configured to apply a voltage to the selection gate line, a switch circuit configured to couple the control gate line to the selection gate line, and a level converting unit coupled to the control gate line and a voltage line and configured to convert a voltage of the control gate line into a voltage of the voltage line.