Invention Grant
US08108762B2 Operating method and circuit for low density parity check (LDPC) decoder
有权
低密度奇偶校验(LDPC)解码器的操作方法和电路
- Patent Title: Operating method and circuit for low density parity check (LDPC) decoder
- Patent Title (中): 低密度奇偶校验(LDPC)解码器的操作方法和电路
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Application No.: US11939119Application Date: 2007-11-13
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Publication No.: US08108762B2Publication Date: 2012-01-31
- Inventor: Chih-Hao Liu , Yen-Chin Liao , Chen-Yi Lee , Hsie-Chia Chang , Yarsun Hsu
- Applicant: Chih-Hao Liu , Yen-Chin Liao , Chen-Yi Lee , Hsie-Chia Chang , Yarsun Hsu
- Applicant Address: TW Hsinchu
- Assignee: National Chiao Tung University
- Current Assignee: National Chiao Tung University
- Current Assignee Address: TW Hsinchu
- Agency: Muncy, Geissler, Olds & Lowe, PLLC
- Priority: TW96128039 20070731
- Main IPC: G06F11/00
- IPC: G06F11/00 ; H03M13/00

Abstract:
An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated check messages and the previous check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. The required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.
Public/Granted literature
- US20090037799A1 OPERATING METHOD APPLIED TO LOW DENSITY PARITY CHECK (LDPC) DECODER AND CIRCUIT THEREOF Public/Granted day:2009-02-05
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