Invention Grant
US08108809B2 Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit
有权
集成电路的路由分析方法,逻辑综合方法和电路划分方法
- Patent Title: Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit
- Patent Title (中): 集成电路的路由分析方法,逻辑综合方法和电路划分方法
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Application No.: US12219371Application Date: 2008-07-21
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Publication No.: US08108809B2Publication Date: 2012-01-31
- Inventor: Toshiyuki Sadakane , Ken Saito , Yoshio Inoue
- Applicant: Toshiyuki Sadakane , Ken Saito , Yoshio Inoue
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: Buchanan Ingersoll & Rooney PC
- Priority: JP2004-132748 20040428
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step 2) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step 1 by a predetermined coefficient α, and a step (Step 3) of calculating a routing difficulty index by dividing the total route length L by the layout area S. Thus, the present invention provides a routing analysis method for an integrated circuit, which, allows calculation of routing difficulty index with high accuracy of prediction.
Public/Granted literature
- US20080295055A1 Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit Public/Granted day:2008-11-27
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