A method and system to improve the performance of an integrated circuit (IC) chip by removing timing violations detected by performing a statistical timing analysis, given distributions of process and environmental sources of variation. The distributions are quantized using a minimum distortion criterion into discrete values. For each timing node of the IC circuit, a discrete minimum and maximum operation is performed on the timing parameters using a subset of combinations of the discrete values. The results of the discrete minimum and maximum operation are then de-quantized and propagated to a subsequent timing node and edge thereof. The process continues until one or more primary inputs and outputs of the IC chip are reached. The design of the IC chip is modified by removing all the timing violations identified.