Invention Grant
- Patent Title: Pattern verification method, method of manufacturing semiconductor device, and recording media
- Patent Title (中): 模式验证方法,制造半导体器件的方法和记录介质
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Application No.: US12420931Application Date: 2009-04-09
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Publication No.: US08108824B2Publication Date: 2012-01-31
- Inventor: Toshiya Kotani , Hiromitsu Mashita , Kazuhito Kobayashi
- Applicant: Toshiya Kotani , Hiromitsu Mashita , Kazuhito Kobayashi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2008-102381 20080410
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A pattern verification method according to an embodiment includes, dividing a pattern data region or a pattern formation region formed based on the pattern data to a plurality of unit regions, calculating a pattern area ratio with respect to each unit region, calculating differences in the amount of the pattern area ratio between each unit region and adjacent unit regions thereto, setting the number or density of measurement point with respect to each unit region to the pattern of the pattern data region or the pattern formation region according to the difference in the amount of pattern area ratio, measuring the pattern size at each measurement point, and verifying whether the size measurement value is within a predetermined range or not.
Public/Granted literature
- US20090258446A1 PATTERN VERIFICATION METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIA Public/Granted day:2009-10-15
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