Invention Grant
US08110440B2 Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure
有权
半导体器件和形成具有共面垂直互连结构的重叠半导体管芯的方法
- Patent Title: Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure
- Patent Title (中): 半导体器件和形成具有共面垂直互连结构的重叠半导体管芯的方法
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Application No.: US12467865Application Date: 2009-05-18
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Publication No.: US08110440B2Publication Date: 2012-02-07
- Inventor: Henry D. Bathan , Zigmund R. Camacho , Jairus L. Pisigan
- Applicant: Henry D. Bathan , Zigmund R. Camacho , Jairus L. Pisigan
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins & Assoiciates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L23/488
Abstract:
A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.
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