Invention Grant
- Patent Title: Manufacturing method of SOI substrate provided with barrier layer
- Patent Title (中): 具有阻挡层的SOI衬底的制造方法
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Application No.: US12211936Application Date: 2008-09-17
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Publication No.: US08110479B2Publication Date: 2012-02-07
- Inventor: Shunpei Yamazaki
- Applicant: Shunpei Yamazaki
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Robinson Intellectual Property Law Office, P.C.
- Agent Eric J. Robinson
- Priority: JP2007-245822 20070921
- Main IPC: H01L21/762
- IPC: H01L21/762

Abstract:
To provide a method for manufacturing a large-area semiconductor device, to provide a method for manufacturing a semiconductor device with high efficiency, and to provide a highly-reliable semiconductor device in the case of using a large-area substrate including an impurity element. A plurality of single crystal semiconductor substrates are concurrently processed to manufacture an SOI substrate, so that an area of a semiconductor device can be increased and a semiconductor device can be manufactured with improved efficiency. In specific, a series of processes is performed using a tray with which a plurality of semiconductor substrates can be concurrently processed. Here, the tray is provided with at least one depression for holding single crystal semiconductor substrates. Further, deterioration of characteristics of a manufactured semiconductor element is prevented by providing an insulating layer serving as a barrier layer against an impurity element which may affect characteristics of the semiconductor element.
Public/Granted literature
- US20090079024A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2009-03-26
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