Invention Grant
US08110486B2 Method of manufacturing semiconductor wafer by forming a strain relaxation SiGe layer on an insulating layer of SOI wafer
失效
通过在SOI晶片的绝缘层上形成应变弛豫SiGe层来制造半导体晶片的方法
- Patent Title: Method of manufacturing semiconductor wafer by forming a strain relaxation SiGe layer on an insulating layer of SOI wafer
- Patent Title (中): 通过在SOI晶片的绝缘层上形成应变弛豫SiGe层来制造半导体晶片的方法
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Application No.: US11649943Application Date: 2007-01-05
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Publication No.: US08110486B2Publication Date: 2012-02-07
- Inventor: Koji Matsumoto , Tomoyuki Hora , Akihiko Endo , Etsurou Morita , Masaharu Ninomiya
- Applicant: Koji Matsumoto , Tomoyuki Hora , Akihiko Endo , Etsurou Morita , Masaharu Ninomiya
- Applicant Address: JP Tokyo
- Assignee: Sumco Corporation
- Current Assignee: Sumco Corporation
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2006-009881 20060118
- Main IPC: H01L21/20
- IPC: H01L21/20
Abstract:
A semiconductor wafer is produced at a step of forming a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer on an insulating layer in a SOI wafer comprising an insulating layer and a SOI layer, wherein at least an upper layer side portion of the SiGe layer is formed on the SOI layer at a gradient of Ge concentration gradually decreasing toward the surface and then subjected to a heat treatment in an oxidizing atmosphere.
Public/Granted literature
- US20070166929A1 Method of producing semiconductor wafer Public/Granted day:2007-07-19
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