Invention Grant
- Patent Title: Integrated circuit packaging system using bottom flip chip die bonding and method of manufacture thereof
- Patent Title (中): 使用底倒装芯片焊接的集成电路封装系统及其制造方法
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Application No.: US12328722Application Date: 2008-12-04
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Publication No.: US08110908B2Publication Date: 2012-02-07
- Inventor: YoungJoon Kim , Ki Youn Jang
- Applicant: YoungJoon Kim , Ki Youn Jang
- Applicant Address: SG Singapore
- Assignee: Stats Chippac Ltd.
- Current Assignee: Stats Chippac Ltd.
- Current Assignee Address: SG Singapore
- Agent Mikio Ishimaru
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/34 ; H01L23/48 ; H01L21/44 ; H01L21/48
Abstract:
A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate cavity; mounting a bottom flip chip die below the substrate; mounting an internal integrated circuit die above the substrate; filling between the internal integrated circuit die and the substrate and between the bottom flip chip die and the substrate with a substance filling through the substrate cavity; and encapsulating the internal integrated circuit die with an encapsulation.
Public/Granted literature
- US20100140769A1 INTEGRATED CIRCUIT PACKAGING SYSTEM USING BOTTOM FLIP CHIP DIE BONDING AND METHOD OF MANUFACTURE THEREOF Public/Granted day:2010-06-10
Information query
IPC分类:
