Invention Grant
- Patent Title: Semiconductor chip package with post electrodes
- Patent Title (中): 具有后置电极的半导体芯片封装
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Application No.: US12864125Application Date: 2009-01-16
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Publication No.: US08110911B2Publication Date: 2012-02-07
- Inventor: Masamichi Ishihara , Hirotaka Ueda
- Applicant: Masamichi Ishihara , Hirotaka Ueda
- Applicant Address: JP Fukuoka
- Assignee: Kyushu Institute of Technology
- Current Assignee: Kyushu Institute of Technology
- Current Assignee Address: JP Fukuoka
- Agency: McGlew and Tuttle, P.C.
- Priority: JP2008-20775 20080131
- International Application: PCT/JP2009/050530 WO 20090116
- International Announcement: WO2009/096250 WO 20090608
- Main IPC: H01L23/22
- IPC: H01L23/22 ; H01L21/00
Abstract:
A first wiring pattern is formed on a surface of a first support plate; a semiconductor chip is disposed on the first wiring pattern; and electrode terminals of the semiconductor chip are electrically connected to the first wiring pattern at required positions. Post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by a second support plate are collectively fixed and electrically connected to the first wiring pattern formed on the first support plate at predetermined positions. After sealing with resin, the first and second support plates are separated; a glass substrate is affixed on a front face side; and external electrodes connected to the second wiring pattern are formed on a back face side.
Public/Granted literature
- US20100295178A1 SEMICONDUCTOR CHIP PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2010-11-25
Information query
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