Invention Grant
- Patent Title: Stacked-type chip package structure and method of fabricating the same
- Patent Title (中): 堆叠式芯片封装结构及其制造方法
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Application No.: US12237035Application Date: 2008-09-24
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Publication No.: US08110928B2Publication Date: 2012-02-07
- Inventor: Chi-Chih Shen , Cheng-Yin Lee , Wei-Chung Wang
- Applicant: Chi-Chih Shen , Cheng-Yin Lee , Wei-Chung Wang
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: J.C. Patents
- Priority: TW96137457A 20071005
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
A stacked-type chip package structure including a first package structure, a second package structure, and a first molding compound is provided. The first package structure includes a first substrate, and a first chip stacked thereon and electrically connected thereto. The second package structure is stacked on the first package structure, and includes a second substrate, a second chip, and a plurality of solder blocks. The second chip is electrically connected to the second substrate, and the second substrate is electrically connected to the first substrate. The second chip is fixed on the first chip through an adhesive layer. The solder blocks are disposed on the back of the second substrate. The first molding compound is disposed on the first substrate and encapsulates the first package structure and the second package structure. The first molding compound has a recess for exposing the solder blocks.
Public/Granted literature
- US20090091015A1 STACKED-TYPE CHIP PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME Public/Granted day:2009-04-09
Information query
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