Invention Grant
US08110933B2 Semiconductor device mounted structure and semiconductor device mounted method
失效
半导体器件安装结构和半导体器件安装方法
- Patent Title: Semiconductor device mounted structure and semiconductor device mounted method
- Patent Title (中): 半导体器件安装结构和半导体器件安装方法
-
Application No.: US12521020Application Date: 2007-12-25
-
Publication No.: US08110933B2Publication Date: 2012-02-07
- Inventor: Yoshihiro Tomura , Daido Komyoji
- Applicant: Yoshihiro Tomura , Daido Komyoji
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: JP2006-349511 20061226
- International Application: PCT/JP2007/074844 WO 20071225
- International Announcement: WO2008/078746 WO 20080703
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L29/40 ; H01L23/29
Abstract:
A recess portion is formed on a board surface at a position facing a peripheral end portion of a semiconductor device so as to place a sealing-bonding resin partially inside the recess portion. Thereby, increases of a placement area for a fillet portion (foot spreading portion) of the sealing-bonding resin are suppressed while its inclination angle is increased. Thus, stress loads that occur to peripheral portions of the semiconductor device due to thermal expansion differences and thermal contraction differences among individual members caused by heating and cooling processes during a mounting operation are relaxed, by which internal breakdown of the semiconductor device mounted structure is avoided.
Public/Granted literature
- US20100025847A1 SEMICONDUCTOR DEVICE MOUNTED STRUCTURE AND SEMICONDUCTOR DEVICE MOUNTED METHOD Public/Granted day:2010-02-04
Information query
IPC分类:
