Invention Grant
- Patent Title: Multi-output determination circuit
- Patent Title (中): 多输出判定电路
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Application No.: US12481152Application Date: 2009-06-09
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Publication No.: US08111061B2Publication Date: 2012-02-07
- Inventor: Kouji Suzuki , Kenichi Takebayashi , Kazutaka Senoo
- Applicant: Kouji Suzuki , Kenichi Takebayashi , Kazutaka Senoo
- Applicant Address: JP Tokyo
- Assignee: Keihin Corporation
- Current Assignee: Keihin Corporation
- Current Assignee Address: JP Tokyo
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2008-152666 20080611
- Main IPC: G01R5/16
- IPC: G01R5/16 ; G01R31/02

Abstract:
An embodiment of the present invention provides a multi-output determination circuit that determines whether or not any one input voltage of a plurality of input voltages is equal to or higher than an upper-limit voltage value. This multi-output determination circuit includes a first diode-OR, upper-limit reference voltage generation means, and a first comparator. The first diode-OR includes a plurality of first diodes whose anodes are each connected to a respective one of the plurality of input voltages and whose cathodes are connected in common. The upper-limit reference voltage generation means has a first resistor, the first diode, and a second resistor that are connected in series between first and second power supply potentials, and generates an upper-limit reference voltage based on the voltage of the cathode of the first diode. The first comparator compares the output voltage of the first diode-OR with the upper-limit reference voltage.
Public/Granted literature
- US20090309575A1 MULTI-OUTPUT DETERMINATION CIRCUIT Public/Granted day:2009-12-17
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