Invention Grant
- Patent Title: Method for evaluating silicon wafer
- Patent Title (中): 硅晶片评估方法
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Application No.: US12448408Application Date: 2007-12-14
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Publication No.: US08111081B2Publication Date: 2012-02-07
- Inventor: Hisayuki Saito
- Applicant: Hisayuki Saito
- Applicant Address: JP Tokyo
- Assignee: Shin-Etsu Handotai Co., Ltd.
- Current Assignee: Shin-Etsu Handotai Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Oliff & Berridge, PLC
- Priority: JP2007-000629 20070105
- International Application: PCT/JP2007/001397 WO 20071214
- International Announcement: WO2008/081567 WO 20080710
- Main IPC: G01R31/34
- IPC: G01R31/34

Abstract:
The present invention is a method for evaluating a silicon wafer by measuring, after fabricating a MOS capacitor by forming an insulator film and one or more electrodes sequentially on a silicon wafer, a dielectric breakdown characteristic of the insulator film by applying an electric field from the electrodes thus formed to the insulator film, the method in which the silicon wafer is evaluated at least by setting an area occupied by all the electrodes thus formed to 5% or more of an area of a front surface of the silicon wafer when the one or more electrodes are formed. This provides an evaluation method that can detect a defect by a simple method such as the TDDB method with the same high degree of precision as that of the DSOD method.
Public/Granted literature
- US20100019796A1 METHOD FOR EVALUATING SILICON WAFER Public/Granted day:2010-01-28
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