Invention Grant
US08111565B2 Memory interface and operation method of it 有权
内存接口及其操作方法

Memory interface and operation method of it
Abstract:
A memory interface includes a first delaying circuit configured to delay write data to be supplied to an input buffer; a second delaying circuit configured to delay read data read out from an output buffer; a data write circuit configured to supply said write data to a memory through said first delaying circuit; and a data read circuit configured to read said write data written in said memory, as said read data through said second delaying circuit. A control circuit is configured to detect positions of a start edge and end edge of an eye opening which is formed based on fluctuation of said write data or said read data, to specify an intermediate position of the start edge and the end edge, and to determine a phase of a data strobe signal based on a difference between the intermediate position and one of the start edge and the end edge.
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