Apparatus and methods are disclosed, such as those involving a memory device. One such memory device includes a memory array including a sub-array that includes a first number of columns of memory cells, and one or more global input/output (I/O) lines shared by the first number of columns for data transmission. The memory device also includes one or more multiplexers/demultiplexers, wherein each of the multiplexers/demultiplexers is electrically coupled to one or more, but not all, of the global I/O lines. The memory device further includes a plurality of local I/O lines, each configured to provide a data path between one of the multiplexers/demultiplexers and one or more, but less than the first number, of the columns in the sub-array. This configuration allows local I/O line repairability with fewer redundant elements, and shorter physical local I/O lines, which translate to improved speed and die size reduction.