Invention Grant
- Patent Title: Adaptive sliding block Viterbi decoder
- Patent Title (中): 自适应滑块维特比解码器
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Application No.: US11755890Application Date: 2007-05-31
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Publication No.: US08111767B2Publication Date: 2012-02-07
- Inventor: Sinan Gezici , Chunjie Duan , Jinyun Zhang , Rajesh Garg
- Applicant: Sinan Gezici , Chunjie Duan , Jinyun Zhang , Rajesh Garg
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: Buchanan Ingersoll & Rooney PC
- Main IPC: H04L
- IPC: H04L

Abstract:
An adaptive sliding block Viterbi decoder (ASBVD) includes forward and backward Viterbi processors, a state estimator and a control unit. The processors generate metrics of states and of transitions between the states associated with an encoder, based on encoded input information symbols received via a communications channel. Each processor includes a plurality of buffers for storing information symbols so that a number of the encoded input information symbols can be concurrently decoded. The state estimator estimates a current state of a code trellis based on the generated metrics, and the processors decode the stored information symbols based on the estimated current state. The control unit adapts the number of encoded input information symbols to be concurrently decoded based on a condition of the communications channel, and selectively controls the number of buffers that are enabled in accordance with the number of encoded input information symbols to be concurrently decoded.
Public/Granted literature
- US20080298513A1 Adaptive Sliding Block Viterbi Decoder Public/Granted day:2008-12-04
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