Invention Grant
US08111796B2 Method and system for switching between two (or more) reference signals for clock synchronization 有权
用于在两个(或多个)参考信号之间切换时钟同步的方法和系统

  • Patent Title: Method and system for switching between two (or more) reference signals for clock synchronization
  • Patent Title (中): 用于在两个(或多个)参考信号之间切换时钟同步的方法和系统
  • Application No.: US12712819
    Application Date: 2010-02-25
  • Publication No.: US08111796B2
    Publication Date: 2012-02-07
  • Inventor: Matthew Duane McShea
  • Applicant: Matthew Duane McShea
  • Applicant Address: US NJ Basking Ridge
  • Assignee: Avaya Inc.
  • Current Assignee: Avaya Inc.
  • Current Assignee Address: US NJ Basking Ridge
  • Agency: Sheridan Ross P.C.
  • Main IPC: H04L7/04
  • IPC: H04L7/04
Method and system for switching between two (or more) reference signals for clock synchronization
Abstract:
An apparatus and method is disclosed for synchronizing a timing signal for a computational system to different reference clock signals without impairing the operation of the computational system. A corresponding “offset” register is provided for each of the reference clock signals (RCS) for storing signal timing differences between the timing signal and RCS. When one of the reference clock signals not used for synchronizing the timing signal, is selected as the signal for synchronizing the timing signal, the corresponding offset register R0 (for the newly selected reference clock signals) retains its last value prior to the switch, and another register R1 stores subsequent signal timing differences between the timing signal and the newly selected reference clock signals. To synchronize the timing signal with the new reference clock signal without distorting the timing signal and impairing the operation of the computation system, differences between R1 and R0 are output (for successive time intervals) for iteratively adjusting the timing signals. The contents of the offset register R0 is incrementally changed toward a predetermined value (i.e., zero) thereby gradually adjusting the timing signals to factor in a potentially large timing change when switching between reference clock signals.
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