Invention Grant
- Patent Title: Apparatus and method for separating a circuit pattern into multiple circuit patterns
- Patent Title (中): 将电路图案分离为多个电路图案的装置和方法
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Application No.: US11889573Application Date: 2007-08-14
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Publication No.: US08111901B2Publication Date: 2012-02-07
- Inventor: Peter Nikolsky
- Applicant: Peter Nikolsky
- Applicant Address: NL Veldhoven
- Assignee: ASML Masktools B.V.
- Current Assignee: ASML Masktools B.V.
- Current Assignee Address: NL Veldhoven
- Agency: Pillsbury Winthrop Shaw Pittman LLP
- Main IPC: G06K9/00
- IPC: G06K9/00

Abstract:
A method for separating an original circuit pattern to be printed on a wafer, into multiple circuit patterns is disclosed. Simulation to obtain an image log-slope (ILS), normalized image log-slope (NILS), or any other characteristic of an image quality on edges of polygons in the circuit pattern obtained from circuit pattern data is performed. Properly printed edges and not-properly printed edges are identified according to a criterion of an ILS level. The original circuit pattern is separated into multiple circuit patterns such that each of the multiple patterns does not have any not-properly printed edges.
Public/Granted literature
- US20080037861A1 Apparatus and method for separating a circuit pattern into multiple circuit patterns Public/Granted day:2008-02-14
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