Invention Grant
- Patent Title: Method and apparatus for inspecting defects of circuit patterns
- Patent Title (中): 检查电路图形缺陷的方法和装置
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Application No.: US11488734Application Date: 2006-07-19
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Publication No.: US08111902B2Publication Date: 2012-02-07
- Inventor: Takashi Hiroi , Naoki Hosoya , Hirohito Okuda , Koichi Hayakawa , Fumihiko Fukunaga
- Applicant: Takashi Hiroi , Naoki Hosoya , Hirohito Okuda , Koichi Hayakawa , Fumihiko Fukunaga
- Applicant Address: JP Tokyo
- Assignee: Hitachi High-Technologies Corporation
- Current Assignee: Hitachi High-Technologies Corporation
- Current Assignee Address: JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2005-250518 20050831
- Main IPC: G06K9/00
- IPC: G06K9/00

Abstract:
The present invention relates to a defect inspection apparatus for inspecting defects in patterns formed on a semiconductor device, on the GUI of which for the confirmation of the inspection results an area is provided for displaying any one of or facing each other the features amount of defects, and the image during inspection or the reacquired image, and on the GUI of which a means is provided for setting the classification class and importance of the defects, and based on the classification class and the importance of the defects information set by this setting means, the classification conditions or the defect judging conditions are automatically or manually set so that the inspection conditions may be set easily.
Public/Granted literature
- US20070047800A1 Method and apparatus for inspecting defects of circuit patterns Public/Granted day:2007-03-01
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