An IC (100) for communicating over a data communication bus (220) comprising a first pair of conductors including a data signal conductor (SDA) and a synchronization signal conductor (SCL), e.g. an I2C bus, is disclosed. The IC comprises a group of address pins (106a-c) for defining the bus address of the integrated circuit (100), each address pin being arranged to be coupled to a conductor from a group of conductors comprising the first pair of conductors and a second pair of conductors including a conductor for carrying a fixed high potential (Vdd) and a conductor for carrying an fixed low potential (GND). The IC (100) further comprises first and second further pins (102, 104) for being coupled to the data signal conductor (SDA) and the synchronization signal conductor (SCL) respectively and a bus address decoder (110) comprising, for each address pin, first means (118) for distinguishing between the first pair of conductors and the second pair of conductors and second means (112, 116) for distinguishing between the conductors belonging to the same pair of conductors. The IC (100) of the present invention provides an area-efficient implementation of an address decoder (110) capable of decoding addresses in an enhanced addressing scheme. In addition, an electronic device (200 comprising a data communication bus (220) and an IC (100) coupled to the data communication bus (220) is disclosed.