Invention Grant
US08112698B2 High speed turbo codes decoder for 3G using pipelined SISO Log-MAP decoders architecture 有权
用于3G的高速turbo码解码器,采用流水线SISO Log-MAP解码器架构

  • Patent Title: High speed turbo codes decoder for 3G using pipelined SISO Log-MAP decoders architecture
  • Patent Title (中): 用于3G的高速turbo码解码器,采用流水线SISO Log-MAP解码器架构
  • Application No.: US12173799
    Application Date: 2008-07-15
  • Publication No.: US08112698B2
    Publication Date: 2012-02-07
  • Inventor: Quang Nguyen
  • Applicant: Quang Nguyen
  • Applicant Address: US DE Wilmington
  • Assignee: ICOMM Technologies Inc.
  • Current Assignee: ICOMM Technologies Inc.
  • Current Assignee Address: US DE Wilmington
  • Agent Bui Garcia-Zamor; Hung H. Bui, Esq.
  • Main IPC: H03M13/03
  • IPC: H03M13/03
High speed turbo codes decoder for 3G using pipelined SISO Log-MAP decoders architecture
Abstract:
A baseband processor is provided having Turbo Codes Decoders with Diversity processing for computing baseband signals from multiple separate antennas. The invention decodes multipath signals that have arrived at the terminal via different routes after being reflected from buildings, trees or hills. The Turbo Codes Decoder with Diversity processing increases the signal to noise ratio (SNR) more than 6 dB which enables the 3rd Generation Wireless system to deliver data rates from up to 2 Mbit/s. The invention provides several improved Turbo Codes Decoder methods and devices that provide a more suitable, practical and simpler method for implementation a Turbo Codes Decoder in ASIC (Application Specific Integrated Circuits) or DSP codes. A plurality of parallel Turbo Codes Decoder blocks is provided to compute baseband signals from multiple different receiver paths. Several pipelined max-Log-MAP decoders are used for iterative decoding of received data. A Sliding Window of Block N data is used for pipeline operations. In a pipeline mode, a first decoder A decodes block N data from a first source, while a second decoder B decodes block N data from a second source during the same clock cycle. Pipelined max-Log-MAP decoders provide high speed data throughput and one output per clock cycle.
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