Invention Grant
- Patent Title: Nanoscale interconnection interface
- Patent Title (中): 纳米级互连接口
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Application No.: US12011175Application Date: 2008-01-23
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Publication No.: US08112700B2Publication Date: 2012-02-07
- Inventor: Philip J. Kuekes , J. Warren Robinett , Gadiel Seroussl , R. Stanley Williams
- Applicant: Philip J. Kuekes , J. Warren Robinett , Gadiel Seroussl , R. Stanley Williams
- Applicant Address: US TX Houston
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Houston
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire addresses to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.
Public/Granted literature
- US20100293518A1 Nanoscale interconnection interface Public/Granted day:2010-11-18
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