Invention Grant
- Patent Title: Contact resistance and capacitance for semiconductor devices
- Patent Title (中): 半导体器件的接触电阻和电容
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Application No.: US12233784Application Date: 2008-09-19
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Publication No.: US08112737B2Publication Date: 2012-02-07
- Inventor: Nagaraj N. Savithri , Dharin Nayeshbhai Shah , Girishankar Gurumurthy
- Applicant: Nagaraj N. Savithri , Dharin Nayeshbhai Shah , Girishankar Gurumurthy
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Warren L. Franz; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F15/04
Abstract:
A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.
Public/Granted literature
- US20090013297A1 CONTACT RESISTANCE AND CAPACITANCE FOR SEMICONDUCTOR DEVICES Public/Granted day:2009-01-08
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