A method of forming a gate of a semiconductor device comprising providing a semiconductor substrate over which a gate insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer are sequentially formed, the semiconductor substrate defining gate line regions; removing he second conductive layer between gate line regions; removing the dielectric layer so that a top surface of the first conductive layer between the gate line regions is exposed; performing a first etch process in order to lower a height of the first conductive layer between the gate line region; removing he dielectric layer between the gate line regions; and, performing a second etch process in order to remove the first conductive layer between the gate line regions.