Invention Grant
US08120106B2 LDMOS with double LDD and trenched drain 有权
LDMOS具有双LDD和沟槽漏极

LDMOS with double LDD and trenched drain
Abstract:
A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening.
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