Invention Grant
- Patent Title: Interconnection of lead frame to die utilizing flip chip process
- Patent Title (中): 引线框架利用倒装芯片工艺互连
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Application No.: US12709000Application Date: 2010-02-19
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Publication No.: US08120154B2Publication Date: 2012-02-21
- Inventor: Mohammad Eslamy , Anthony C. Tsui
- Applicant: Mohammad Eslamy , Anthony C. Tsui
- Applicant Address: US CA Santa Clara
- Assignee: GEM Services, Inc.
- Current Assignee: GEM Services, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
Embodiments in accordance with the present invention relate to techniques which avoid the problems of deformation in the shape of a solder connection in a flip chip package, resulting from solder reflow. In one embodiment, a solder-repellent surface is created adjacent to the solder to constrain the reflow and thereby maintain the vertical profile of the solder. Examples of such a solder-repellent surface include an oxide (such as Brown Oxide) of the lead frame, or a tape (such as Kapton) which is used as a dam bar to control/constrain the solder flow on the leads prior to the encapsulation step. In another embodiment, the solder connection may be formed from at least two components. The first component may reflow at high temperatures to provide the necessary adhesion between solder ball and the die, with the second component reflowing at a lower temperature to provide the necessary adhesion between the solder ball and the leads. An example of such multi-component connections include a first high temperature reflow solder ball paired with a second low temperature reflow solder. Another example includes a solder ball with a hard core (such as Cu, stainless steel, or a plastic material stable at high temperatures) coated with a lower temperature reflow material.
Public/Granted literature
- US20100140762A1 INTERCONNECTION OF LEAD FRAME TO DIE UTILIZING FLIP CHIP PROCESS Public/Granted day:2010-06-10
Information query
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