Invention Grant
- Patent Title: Package with improved connection of a decoupling capacitor
- Patent Title (中): 具有改进的去耦电容器连接的封装
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Application No.: US11904752Application Date: 2007-09-28
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Publication No.: US08120162B2Publication Date: 2012-02-21
- Inventor: Jitesh Shah
- Applicant: Jitesh Shah
- Applicant Address: US CA San Jose
- Assignee: Integrated Device Technology, Inc.
- Current Assignee: Integrated Device Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Roeder & Broder LLP
- Main IPC: H01L29/00
- IPC: H01L29/00

Abstract:
A package (216) for electrically connecting an integrated circuit (212) to a printed circuit board (214) includes a mount array (219) and a substrate body (216A). The mount array (219) is electrically connected to the integrated circuit (212). The mount array (219) includes a plurality of positive terminal mounts (342), a plurality of negative terminal mounts (344), and a plurality of signal mounts (346). The substrate body (216A) includes a first conductive layer (220a), a second conductive layer (220b), and an insulating layer (222a) that is positioned between the first conductive layer (220a) and the second conductive layer (220b). The first conductive layer (220a) includes (i) a terminal portion (350) that is connected one of the terminal mounts (342) (344), and (ii) a signal portion (352) that is connected to the signal mounts (346). Further, the second conductive layer (220b) is directly connected to the other of the terminal mounts (344) (342). Additionally, the package (216) can include a capacitor (238) having a positive capacitor pad (556) and a negative capacitor pad (554). The electrical path of the capacitor (238) to the mount array (219) in the designs provided herein is relatively short, has relatively low impedance, and has a relatively low loop inductance.
Public/Granted literature
- US20090085158A1 Package with improved connection of a decoupling capacitor Public/Granted day:2009-04-02
Information query
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