Invention Grant
US08120183B2 Method of forming top electrode for capacitor and interconnection in integrated passive device (IPD)
有权
在集成无源器件(IPD)中形成电容器和互连顶电极的方法
- Patent Title: Method of forming top electrode for capacitor and interconnection in integrated passive device (IPD)
- Patent Title (中): 在集成无源器件(IPD)中形成电容器和互连顶电极的方法
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Application No.: US12763386Application Date: 2010-04-20
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Publication No.: US08120183B2Publication Date: 2012-02-21
- Inventor: Yaojian Lin , Robert C. Frye
- Applicant: Yaojian Lin , Robert C. Frye
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins & Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/52
- IPC: H01L23/52

Abstract:
A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.
Public/Granted literature
- US20100200951A1 Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD) Public/Granted day:2010-08-12
Information query
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