Invention Grant
US08120389B2 Digital to frequency synthesis using flying-adder with dithered command input
有权
数字频率合成使用飞加法器与抖动命令输入
- Patent Title: Digital to frequency synthesis using flying-adder with dithered command input
- Patent Title (中): 数字频率合成使用飞加法器与抖动命令输入
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Application No.: US12536181Application Date: 2009-08-05
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Publication No.: US08120389B2Publication Date: 2012-02-21
- Inventor: Liming Xiu
- Applicant: Liming Xiu
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: H03B21/00
- IPC: H03B21/00 ; H03L7/06

Abstract:
To make Flying-Adder architecture even more powerful, a new concept, time-average-frequency, is incorporated into the clock generation circuitry. This is a fundamental breakthrough since it attacks the clock generation problem from its root: how is the clock signal used in real systems? By investigating from this direction, a much more powerful architecture, fixed-VCO-Flying-Adder architecture, is created. Furthermore, based on fixed-VCO-Flying-Adder frequency synthesizer and time-average-frequency, a new type of component called Digital-to-Frequency Converter (DFC) is born.
Public/Granted literature
- US20110285439A1 Digital to Frequency Synthesis Using Flying-Adder with Dithered Command Input Public/Granted day:2011-11-24
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