Invention Grant
US08120939B2 ROM cell having an isolation transistor formed between first and second pass transistors and connected between a differential bitline pair 有权
ROM单元具有形成在第一和第二通过晶体管之间并连接在差分位线对之间的隔离晶体管

ROM cell having an isolation transistor formed between first and second pass transistors and connected between a differential bitline pair
Abstract:
A semiconductor memory cell array includes an elongated continuous active region. First and second pass transistors are formed in the elongated continuous active region and form part of first and second adjacent memory cells, respectively, of a column of memory cells in the array. An isolation transistor is formed in the elongated continuous active region between the first and second pass transistors and biased in an off state. First and second word lines are coupled to the gates of the pass transistors for applying a reading voltage. The array includes a differential bit line pair including first and second bit lines, a first logic value being encoded into the memory cells by connecting the pass transistors to the first bit line and a second logic value being encoded into the memory cells by connecting the pass transistors to the second bit line.
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