Invention Grant
US08120987B2 Structure and method for decoding read data-bus with column-steering redundancy
有权
使用列转向冗余解码读数据总线的结构和方法
- Patent Title: Structure and method for decoding read data-bus with column-steering redundancy
- Patent Title (中): 使用列转向冗余解码读数据总线的结构和方法
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Application No.: US12652345Application Date: 2010-01-05
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Publication No.: US08120987B2Publication Date: 2012-02-21
- Inventor: Howard Pilo , Vinod Ramadurai
- Applicant: Howard Pilo , Vinod Ramadurai
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent David A. Cain
- Main IPC: G11C8/00
- IPC: G11C8/00

Abstract:
A random access memory circuit enabling a decodable sense amplifier array for power saving with column steering redundancy. A first decoder receives an input address and accesses at least one memory cell in the array and is capable of executing column steering redundancy. A master redundancy signal is triggered when column steering redundancy is requested. A plurality of sense amplifiers, wherein, each sense amplifier in the plurality of sense amplifiers is coupled to at least one memory cell in an array of memory cells. A second decoder receives the input address and selectively activates a first set of sense amplifiers of the plurality of sense amplifiers and selectively activates a second set of sense amplifiers in the plurality of amplifier only when the master redundancy signal is activated.
Public/Granted literature
- US20110164463A1 Structure and Method for Decoding Read Data-Bus With Column-Steering Redundancy Public/Granted day:2011-07-07
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