Invention Grant
- Patent Title: Concurrent multiple-dimension word-addressable memory architecture
- Patent Title (中): 并行多维字符寻址存储器架构
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Application No.: US11767639Application Date: 2007-06-25
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Publication No.: US08120989B2Publication Date: 2012-02-21
- Inventor: Chihtung Chen , Inyup Kang , Viraphol Chaiyakul
- Applicant: Chihtung Chen , Inyup Kang , Viraphol Chaiyakul
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Sam Talpalatsky; Nicholas J. Pauley; Jonathan T. Velasco
- Main IPC: G11C7/10
- IPC: G11C7/10
Abstract:
An N-dimension addressable memory. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
Public/Granted literature
- US20080316835A1 Concurrent Multiple-Dimension Word-Addressable Memory Architecture Public/Granted day:2008-12-25
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