Invention Grant
US08122311B2 Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules processing data signals at different rates
有权
在具有以不同速率处理数据信号的可选模块的系统中的JTAG测试中用于时钟信号同步的装置和方法
- Patent Title: Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules processing data signals at different rates
- Patent Title (中): 在具有以不同速率处理数据信号的可选模块的系统中的JTAG测试中用于时钟信号同步的装置和方法
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Application No.: US13007278Application Date: 2011-01-14
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Publication No.: US08122311B2Publication Date: 2012-02-21
- Inventor: Gary L. Swoboda
- Applicant: Gary L. Swoboda
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Mima Abyad; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the combiner unit, the combiner unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an combiner unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the combiner unit.
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