Invention Grant
- Patent Title: Error detector and error detection method
- Patent Title (中): 误差检测器和误差检测方法
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Application No.: US11976544Application Date: 2007-10-25
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Publication No.: US08122316B2Publication Date: 2012-02-21
- Inventor: Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
- Applicant: Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
- Applicant Address: JP Kobe-shi JP Yokohama-shi JP Kawasaki-shi
- Assignee: Fujitsu Ten Limited,Fujitsu Semiconductor Limited,Renesas Electronics Corporation
- Current Assignee: Fujitsu Ten Limited,Fujitsu Semiconductor Limited,Renesas Electronics Corporation
- Current Assignee Address: JP Kobe-shi JP Yokohama-shi JP Kawasaki-shi
- Agency: Oliff & Berridge, PLC
- Priority: JP2006-293371 20061027
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G06F11/00 ; G06F11/30 ; G08C25/00 ; H04L1/00

Abstract:
An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
Public/Granted literature
- US20080141074A1 Error detector and error detection method Public/Granted day:2008-06-12
Information query
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