Invention Grant
US08122408B2 Circuit verification method for verifying circuit with timing information and logic information in library cell
有权
用于在库单元中验证具有定时信息和逻辑信息的电路的电路验证方法
- Patent Title: Circuit verification method for verifying circuit with timing information and logic information in library cell
- Patent Title (中): 用于在库单元中验证具有定时信息和逻辑信息的电路的电路验证方法
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Application No.: US12591880Application Date: 2009-12-03
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Publication No.: US08122408B2Publication Date: 2012-02-21
- Inventor: Hirokazu Hatori
- Applicant: Hirokazu Hatori
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-313641 20081209
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50
Abstract:
A circuit verification method propagates a fixed logic value from a black-box circuit block without logic information to a subsequent-stage circuit, by taking into consideration timing information.
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